Staffing-Human Resources at Xilinx
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Xilinx - Senior Design Verification Engineer - System Verilog/Verilog (6-12 yrs)
- BS w/ 7+ years or MS w/ 5+ years in Electrical Engineering, Computer Engineering, or Computer Science
- Experienced with development of System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level designs
- Good understanding of different phases of verification flow
- Experience with developing tools from scratch using Python, Perl. Familiar with Python, Perl GUI based toolkit development.
- Strong object oriented software techniques. Should have written code using software OOP techniques not just writing simple scripts
- Should have good software debug skills,
- Knowledge of GUI based development toolkits like Qt or Java is a plus
- Experienced with using shell scripts like bash, tcsh and very familiar writing Makefiles
- Very familiar with version control tools like Perforce, Clearcase or Cvs
- Experience coding using C/C++ is a plus. Should have done some programming using C or C++
- Experience with using planning and tracking tools like JIRA, Bugzilla is a plus
- Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.