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10/10 Ravi Kiran Balla
Human Resources at Xilinx

Views:25 Applications:1 Rec. Actions:Recruiter Actions:0

Xilinx - RTL Design Engineer - Verilog/System Verilog (5-15 yrs)

Hyderabad Job Code: 502146

Requirements :

- Bachelors or Masters in Electrical/Electronics engineering

- Strong academic background

- Strong logic design concepts and computer design

- Expertise in Verilog, VHDL and exposure to industry simulators

- Expertise in front end RTL design flow steps like lint, CDC, STA etc

- Expertise in IP & System design

- Experience in Storage Solution development

- Experience with Xilinx Tools & Devices

Women-friendly workplace:

Maternity and Paternity Benefits

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