Recruitment Specialist at Xilinx
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Xilinx - IP Verification Engineer - UVM/OVM (5-10 yrs)
Job Description: Design concepts, Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers, Phy Layer Knowledge
- Strong working knowledge of SV under UVM guidelines, UNIX environment and scripting languages such as Perl or Python, Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim
- Experience using UNIX Revision Control tools - Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla
- Experience in verifying multimillion gate chip designs from specifications to tape-out.
- Mixed Signal verification Knowledge would be an added advantage.