Staffing-Human Resources at Xilinx
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Xilinx - DDR Verification Engineer - Memory Controllers (5-15 yrs)
- Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.
- Proven track record on driving strategies and successful verification execution on Memory Controllers (HBM Gen 1/2, DDR3/4, LPDDR3/4, RLDRAM3, QDR2+, QDRIV), high performance IPs and/or SOC designs.
- Proven track record in technical leadership of teams of 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
- Hands on experience with verification of state of the art memory controllers such as HBM, DDR, LPDDR, RLDRAM and QDR. Requires strong understanding of current memory controller protocols and calibration (HBM Gen1/2, DDR3/4, LPDDR3/4, RLDRAM3, QDR2, QDRIV), JEDEC specification, board skew and jitter modeling.
- Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
- Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
- Experience with FPGA programming and software is a plus.
- Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.