30/04 Sapna
Recruitment Consultant at IT Trailblazers

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WiFi IP ASIC Design Specialist/Lead - System Verilog (4-14 yrs)

Chennai Job Code: 438648

As a design engineer you will work on developing IPs catering to upcoming WiFi standards like 802.11ax and beyond. You will have opportunity to contribute to the life cycle of the technology right from IP specification, till productization/customer deployments, leveraging your verification, pre and post silicon debug expertise.

Skills/Experience :


- 4 to 12 years of direct related industry experience in ASIC / SoC - SystemVerilog, Verilog for design.

- Decent knowledge with any or one of these Radio standards: IEEE WLAN 802.11 a/b/g/n/ac/ad/ah/ax will be an added advantage.

- Must have hands-on experience and expert level knowledge on RTL design, Linting, CDC, UPF, CPF and other Low power tools, Post and Pre Silicon bring up trouble shooting.

- Extensive architectural knowledge of high-performance bus protocols such as AHB and AXI

- Scripting language like Perl, Python

- Good analytical and Debugging skills

Responsibilities :

- Responsible for RTL design/development of wireless MAC subsystem blocks, micro-architecture of specifications from IEEE spec, work closely with verification team to develop verification plans and actively participate in debug phase.

- Will work hands-on and own the design through the full ASIC development process from specification, RTL implementation, verification, synthesis timing closure, emulation and post silicon bring up.

- Will be contributing to our Wireless connectivity business for RTL implementation of WLAN MAC Design, SOC


- Digital design, Micro architecture and RTL coding in Verilog, High-level / Mid-Level / Low-level Design reviews.

- Writing and maintaining MLDs, HLDs and SWI documentation, ASIC Frontend Tools: Linting, Formal Logic equivalence, Logic synthesis, STA, CDC checks

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