HR Executive at Indium Global Services
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VLSI Verification Engineer - System Verilog (6-20 yrs)
- A strong experience in block design and IP verification within digital ASIC.
- Good experience in SystemVerilog and UVM Methodology based verification
- Minimum of 5+ Years of ASIC Verification experience
- Good command on English both in written and spoken, Swedish language knowledge is an advantage
- You should have Positive attitude, social skills, a desire to help team members, structured way of working and an eye for quality work.
- You enjoy working both independently and in a small diverse and you are focused on reaching result on time.
- The work will be carried out in a cross functional team using Scrum/Agile ways of working
Skills Required :
- Design verification Skills
- Miscellaneous tasks in connection to the block design
- Verification planning
- Verification specification
- Verification environment (creation/adaptation/maintenance).
- Verification documentation
- Test case creation
- Usage of reference models
- Constrained random testing
- Creation of Coverage matrix
Preferred : Experienced in WCDMA, GSM and/or LTE systems.
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