VLSI Physical Designer - Floor Planning/Synthesis/SoC (2-12 yrs)
Job Description :
Exp : 2- 10Yrs
Location : Bangalore
- Implementation of multimillion gate SoC designs in cutting edge process technologies (65nm, 40nm, 28nm& below ).
- Strong Hands-on expertise on any of the aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
- Expertise in Synopsys IC compiler, Magma or Cadence SOC encounter physical design tools.
- Skill and experience in scripting using Tcl or Perl is highly desirable
Interested candidates can apply here.
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