Associate Recruiter at UST Global
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VLSI/PD STA Engineer - Timing Closure (4-10 yrs)
Designation : STA/Synthesis Design Engineer /Lead Engineer/Engineering Manager.
Skill : STA / Synthesis
Experience : 2 to 10 years
Job location : Bangalore
No. of Position : 30
Technology : 7nm/14nm/16nm/28nm
Tools : Design Compiler/Genus/Prime time/Tempus
Job Description :
- Exposure to Synthesis, static timing analysis (STA) and timing sign-off
Experience with :
- Low power design techniques and checks
- Responsible for floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis and Physical Verification of Low power and high frequency designs.
- Logical equivalence checks (in Formailty or LEC)
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