Semiconductor Recruiter at Swedium Global Services
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VLSI Design Engineer- STA/Synthesis (5-12 yrs)
- Experience in ASIC, SoC or FPGA logic design.
- Experience in STA and Synthesis
- Expert in VHDL/Verilog/System Verilog
- Excellent knowledge of: DC/PC/ICC1/ICC2
- Synthesis experience for Timing/Area/Power closure multi Core CPU Architecture Knowledge
- Experience in using TCL/Python/Perl/etc.
- Have worked with Environment like Linux, ClearCase, LSF