24/07 Madhavi
BDM at Consign Dimension

Views:655 Applications:57 Rec. Actions:Recruiter Actions:24

VLSI Design Engineer - Floor Planning (2-8 yrs)

Bangalore Job Code: 345370

Required RTL Admin,Chip Designer,Physical Designer,Verilog,Verification,Td,Dsp

Location : bangalore

Job Description :

Skills Required :

- Block level floor planning, power planning and IR drop analysis.

- Timing closure with Xtalk and OCV

- Multimode multi corner optimization and closure.

- Clock tree synthesis and advanced clock tree implementation.

- Blocks sizes upward of 400K Instances to 2M Instances.

- Block level timing closure with sign off STA.

- Block level ECO implementation involving netlist level logical changes.

- Scripting experience in Perl/TCL.

- Excellent debugging skills in implementation issues and ability to come up with creative solutions.

- Low power technologies exposure.

- Technologies from 28nm and below.

- Physical Verification experience in advance nodes.

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