IT Recruiter at Infinity HR Consulting Pvt Ltd
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VIP Verification Engineer - Verilog/System Verilog (3-10 yrs)
Please go through JOB Description before applying:
Job Duties
- Be an integral part of the team that verifies VIP product for bus standard interfaces such as PCIe4/5, USB3.1, 400Gigabit Ethernet, DRAM, Flash memories and leading AMBA coherency protocols like ACE, CHI for use with Questa RTL simulation.
- Questa verification IP's help design teams find more bugs in less time than conventional simulation techniques.
- Having deep protocol understanding, you will be responsible for creating extensive validation tests suite covering full protocol scenarios
- Integrate VIP with a real design and create test bench that is flexible to configure in all possible use models
- Validate VIP using design IP for functional correctness. Work with IP vendors to get design issues resolved
- 100% Assertions and code coverage, test all possible error scenarios from protocol
- Work on verifying various usability, debug aspects, performance of VIP
- You will interact with TMEs, field, factory across different locations as part of job role
- Participate in analysis of the problems reported by customers (improve test suite)
- Mentor and guide the junior engineers for better delivery of the project
Job Qualifications :
- B.Tech/ M.Tech in electrical engineering or related field from reputed institute
- Sound Verilog HDL RTL knowledge and working knowhow of RTL simulations
- Sound knowhow of System Verilog for testbench with exposure to verification methodologies like UVM, VMM etc.
- Intimate knowledge of one or more standard bus protocols, like PCIe, USB, Ethernet, SATA, NVMe, DRAM, Flash etc.
- Should be process oriented and have a passion for scripting/automation
- Good debug skills
- 3-10 years of experience in verification engineering
Desired skills & experience :
- Protocol expertize in one or more of the protocol - PCIe, Ethernet, USB2/3, DRAM
- SV, UVM
- Experience in creating UVM based testbench and verification using constrained random stimulus
