03/06 Roopa
HR Manager at Redpine Signals, Inc.

Views:192 Applications:9 Rec. Actions:Recruiter Actions:3

Verification Lead Engineer - RTL Design (5-10 yrs)

Hyderabad Job Code: 451282

Experience level : 5 to 10 years

We require experience in :

- RTL Design

- SoC subsystems

- Processor architecture

- SV Testbenches and Advanced Verification Environments

- Test plan development and Verification Coverage

- Bus protocols

- Gate level simulation, emulation, FPGA prototyping

Education Requirements : B.Tech / M.Tech / MS

Women-friendly workplace:

Maternity and Paternity Benefits

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