Recruiter at Shellinfotech
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Verification Engineer - UVM/VMM/OVM (3-12 yrs)
- Strong on System Verilog and Verification Methodologies such as UVM/VMM/OVM.
- Capable of independently defining test plans, developing new constrained random test cases, debugging and enhancing existing test cases.
- Capable of developing verification environment components such as end-to-end checkers/scoreboards, monitors, functional coverage etc.
- Experienced in atleast one of the following high speed interconnects such as USB 3.0, MIPI Unipro, PCIe, SATA, RIO etc
- And Strong domain knowledge on USB, MIPI, AMBA protocols.