Associate Researcher - HR at eHireo Global Pvt Ltd
Views:266 Applications:14 Rec. Actions:Recruiter Actions:2
Verification Engineer - System Verilog/UVM/VMM (3-7 yrs)
Job description :
Looking for candidates with experience in GPU/CPU pipeline, memory subsystem (cache coherency, etc) and UVM methodology (OR)People with 6+ years in SV and UVM.
Responsibilities Include :
- Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers. Review unit level test plans; modify if necessary. Write the tests outlined by test plan.
- Enhance test bench if necessary, e.g. add coverage assertions.
- Enhance test benches and tests to achieve coverage goals. Support debug of unit in upper levels of design hierarchy.
Experience Requirements :
- Has used modern verification methodologies such UVM/VMM/OVM. UVM is preferred.
- Experience verifying and debugging RTL, preferably in context of CPU, GPU, video,display or signal processing system.
- Understanding of micro-architecture and logic design fundamentals, e.g. finite state machines, arithmetic data path pipelines. Composed functional coverage assertions, preferably using system Verilog.
The qualified candidate will possess the following : BSEE or higher degree. At least 5 years of industry experience in a design verification role.
Proficient in : System Verilog. C++, Python/Perl skills are also desirable provided by Dice Verilog,UVM,SV,System Verilog,OVM
This job opening was posted long time back. It may not be active. Nor was it removed by the recruiter. Please use your discretion.