17/07 Divya Rao
Senior Talent Acquisition Specialist at Vipsa Talent Solutions

Views:83 Applications:11 Rec. Actions:Recruiter Actions:3

Verification Engineer - System Verilog/UVM (6-13 yrs)

Bangalore Job Code: 468873

SOC Verification Engineer

Qualification : BE/BTech, ME/MTech ( VLSI Domain )

Job Description :

- Development of verification plans

- Verification environments

- Test cases and ensuring coverage and performance goals are achieved for IP and SOC level

- Working Knowledge of ARM processors.

- HVLs/Tools : System Verilog, UVM - Universal Verification Methodology, C language

Domain : 


- Networking, Memory DDR2/3/4, Ethernet PCIe,

- IP Verification Engineer

Qualification : BE/BTech, ME/MTech ( VLSI Domain )

Job Description :

- Strong System Verilog or Specman expertise OVM/UVM/eRM expertise highly desired

- Good knowledge of protocols

- Ability and desire to learn new methodologies, languages, protocols etc

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