28/06 Himani Sharma
Researcher at New Era India

Views:112 Applications:7 Rec. Actions:Recruiter Actions:2

Verification Engineer - System Verilog/UVM (4-10 yrs)

Bangalore/Hyderabad Job Code: 461335

Key responsibilities and requirements for this position are to :

- Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support

- Understand the competitive landscape and continuously work on differentiating Cadence's solutions.

- Experience with SV/UVM - Must

- Experience with Cadence Verification IP - Advantage

- Experience with protocols - PCIE, Eth, MIPI, USB - Advantage

- Experience with Cadence Xcelium/Incisive, MDV and/or vManager - Advantage

- Experience with embedded SW, coding of Firmware or drivers - Advantage

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