24/07 Madhavi
BDM at Consign Dimension

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Verification Engineer - System Verilog/ARM/UVM (2-6 yrs)

Bangalore/Chennai/Hyderabad Job Code: 345373

1. Develop and integrate subsystems.

2. Methodology (OVM/UVM).System Verilog(UVM), Mat lab

3. Xilinix - Altera

4. Tools : VCS. Model : Questa

5. Ip Verification : PCI Express,Ethernet,ARM, AHB/AXI, DDR, UART .

- Development of verification plan (Vplan)

- Extensive knowledge in VHDL and Verilog

- Extensive Verification knowledge using SystemVerilog/UVM and/or e/Specman

- Good VIP (Verification IP) design knowledge

- Good System Verilog assertions knowledge

- Analysis of Code coverage

- Managing and debugging regressions

- Evaluate regressions and mapping to Vpla

6. Job Title : FPGA Design Engineer

Years of Exp : 3 - 6 Years

Job Description :

- ASIC/FPGA Designer Profile

- Extensive experience in RTL coding using Verilog,

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