HR Executive at Swedium Global Services AB
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Verification Engineer - System Verilog (5-20 yrs)
Responsibilities & Tasks :
- To develop test cases and/ or test framework.
- To develop verification components using System Verilog.
- To execute and debug test cases.
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent education.
- Should have at least 5 years of relevant work experience.
- Experience from software driven top level verification of ASICs.
- Should have good understanding of VHDL or System Verilog.
- Should have experience in C programming
- Good to have experience in verification of high speed interfaces or in ARM CPU subsystems.
- Experience in scripting languages (Python, Perl, Linux Shell scripting etc.)
- Experience with mobile communication standards is an advantage.
- You will have to participate in daily and periodic agile meetings also to do documentation for verification specification and reports.