Verification Engineer - RTL Design/C/C++ (5-14 yrs)
- Working experience in functional verification.
- Hands on experience on developing source code with reasonable complexity.
- Experience developing and working with object-oriented verification languages (System Verilog, VMM, OVM, UVM)
- A solid understanding of object-oriented concepts and experience designing class-based test benches.
- Knowledge of Industry Standard Protocols like Ethernet, PCIe, MIPI, DDR, AXI-AHB Bus or any other protocol will be added advantage.
- Knowledge of OCP, AXI-ACE, and NoC would be desirable.
- Verification of Complex RTL Design IP/ SoC at module level and system level.
- Strong debugging skills
- Strong C/C++, Perl, and scripting skills
- Knowledge of handing VIPs usage in UVM flow
- Working knowledge of EDA Tools(NCSim, VCS, QuestaSim)
- Knowledge on FPGA Architectures
- Must have handles IP verifications of relative complexities of USB, PCIe etc.
- Strong understanding of typical design structures (FIFOs, pipelines, memories, state machines, etc.)
- Comfortable and confident interacting with customers
- Excellent written and oral communication skills
- Highly motivated and independent contributor with good aptitude and attitude.