11/12 Shankar
Recruiter at Freelancer

Views:97 Applications:5 Rec. Actions:Recruiter Actions:0

Verification Engineer - Mixed Signal/System Verilog (5-8 yrs)

Anywhere in India/Multiple Locations Job Code: 389704

- Looking for suitable engineers with 5+ years of experience in

- SOC/IP/Sub-System Design Verification

- Strong hands-on individual contributors.

- Be able and willing to work in a team environment.

- Be able to support periodic training session and knowledge sharing sessions.

- Strong debug skills and Automation savvy.

- Good understanding of ARM (and or DSP) architecture

- Good understanding of mixed-signal building blocks and their verification

- Understanding of power management and its implication on verification

- Test plan creation capturing all the functional requirements

- Create, debug and validate all the test possibilities

- Create IP and SOC test benches

- Coverage (code & test cases) metric based verification sign-off

- Good understanding of Gate-Level simulations and its nuances

- Translate test cases to ATE platform to validate functionality & timing

- Be able to help in silicon debug both on ATE and at system level

- Failing test cases

- Test case marginalities

- Timing characterization

- Functional issues

- Good knowledge of verilog, SystemVerilog VMM/UVM/C CPF,UPF

- Good knowledge of any of the simulation tools/environments

Add a note
Something suspicious? Report this job posting.