Verification Engineer - Mixed Signal/Netlist (4-12 yrs)
- Hands on experience in Analog mixed signal/Mixed mode Verification
- Leading and mentoring technical team of 4 to 6 members to execute Complete verification cycle.
- Must have HANDS ON EXPERIENCE simulating SPICE, SPECTRE netlists and RTL.
- Strong knowledge and experience in RTL verification test bench creation using Verilog/System Verilog and UVM.
- Tool experience AMS Designer, VCS-AMS or similar mixed signal simulators
- Lead must have experience in verifying multiple successful full chip /IP
- Domain knowledge on SERDES/USB/SATA/DDR/PCI is plus