08/05 Divya Prasanna
Talent Acquisition Member at SVENTL ASIA PEC LTD

Views:240 Applications:7 Rec. Actions:Recruiter Actions:0

Verification Engineer/Lead Engineer - ASIC/Verilog/System Verilog (4-9 yrs)

Bangalore/Chennai/Hyderabad/Noida/Singapore Job Code: 441493

Job Location : Singapore.

Experience : 4-9 Years

Job Role : Verification Engineer/Lead Engineer.

- Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level

- Develop IP level/SoC level test plans based on the design/architectural specs.

- Coverage Analysis and Coding

- Run simulations & regressions, debug test failures to identify test case issues & RTL design issues

- Define and develop block/full chip level verification environment and its components

Required Skills:

- 4 & above years of experience in ASIC Verification and Methodologies

- Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies

- Good understanding of RTL concepts

- Good understanding of AHB/AXI protocol

- Expertise in PCI-e/ USB/ Ethernet/ Switch/MAC/FAC/Serdes protocol is an added advantage

- Knowledge of Perl/TCL is Must

- Good communication skill

Women-friendly workplace:

Maternity and Paternity Benefits

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