17/07 Pallavi Joshi
Director at Beafirm Infotech Private Limited

Views:100 Applications:22 Rec. Actions:Recruiter Actions:5

Verification Engineer - DSP (2-8 yrs)

Bangalore Job Code: 469050

Please share cv if looking for job change in below profiles.

1. CPU verification

- Design verification of CPU IP by working with a global DSP design team involving architecture, implementation, post silicon and back-end teams

- Processor Architecture and Processor Verification

- Implement and improve System Verilog Testbench Architecture, assertions, coverage

- Experience in VERA/System Verilog, simulators from Synopsys/Mentor/Cadence

2. Power Aware Verification :

- Power aware design verification of DSP IP by working with a global DSP design team involving architecture, implementation, post silicon and back-end teams

- Implement and improve System Verilog Testbench Architecture, assertions, coverage

- Expertise in UPF based power aware verification

- Experience in VERA/System Verilog, simulators from Synopsys/Mentor/Cadence

3. GLS Verification:

- Responsible for, gate level simulation bring up, gate level verification

- 0-delay and SDF gate level simulations

- Experience in VERA/System Verilog, simulators from Synopsys/Mentor/Cadence

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