11/06 Kamal D
Senior Career Consultant at Teamlease

Views:451 Applications:23 Rec. Actions:Recruiter Actions:3

Verification Engineer - ASIC/SOC (3-6 yrs)

Bangalore/Hyderabad Job Code: 332632

We are looking for ASIC/SOC Verification Enginner with one of our Semiconductor client in Bangalore and Hyderabad.

Designation : ASIC/SOC verification Engineer

Job Description :

Qualification : Bachelors or Masters (Computer/Electronics Engineering)

Experience : 3 - 6 years

Job Location : Bangalore & Hyderabad

- As a part of the verification team, ASIC/SoC Verification engineers are responsible for implementing the verification models, integrating the verification environments, develop script based utilities and support verification activities.

The key functions and responsibilities are the following :

- Define and Implement the ASIC/SoC verification environment

- Develop block and system-level test benches and verification environments using Verilog/SystemVerilog, C/C++, SystemC, VMM/OVM/UVM and/or other verification languages as appropriate.

- Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.

- Work with design and verification teams and provide technical support for verification activities.

- Support the development of verification test plans, test suites and verification activities

Essential Technical Expertise :

- Experience in ASIC/SoC verification activities and should have participated in successful completion of at least one ASIC/SoC project from Specifications to Silicon.

- Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or moreembedded processor based SoC. Good understanding of ARM processor architecture is plus.

- Must be knowledgeable on ASIC verification methodologies and levels functional, RTL, gate level, Low power and processor verification.

- Must have experience in developing BFM and functional models in Verilog/System Verilog/ OVM/VMM/UVM.

- Proven experience of the design verification methodologies such as VMM/OVM/UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.

- Must have experience in Make and proficient in scripting using perl, Tcl,etc.

- Must have worked on developing verification environment and test cases.

- Must have conducted functional simulations, exposure to functional coverage and bug management schemes.

- Protocol Knowledge on PCIe, USB2.0/3.0, Ethernet and LPDDR2/DDR3 is added advantage.

- Self-motivation, flexibility, with strong inter-personal skills.

- Good communication skills, oral and written.

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