23/08 Madhavi
BDM at Rishyaa Digicorp

Views:281 Applications:39 Rec. Actions:Recruiter Actions:8

Verification Engineer - ASIC/RTL/Verilog (3-10 yrs)

Bangalore/Hyderabad Job Code: 483820

Design Requirements [3-5 Years - 8 positions; 5-10 Years - 2 positions]

Job Description :

Responsibility :

Candidate will be responsible for running the implementation flows like PLDRC(Spyglass - Pre Layout Design Rule Checks), CDC(0-in CDC Clock Domain Crossing) and Low Power flows( CLP, Unified Power Flow), Sanity simulations runs and release flows to SoC.

Skills/Experience :

- 3-10 years of experience in ASIC development

- Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)

- Experience in formal verification with Cadence LEC

- Experience in Spyglass Lint/CDC checks and waiver creation

- Experience in RTL HDL languages Verilog/VHDL

- Understanding of RTL to GDS flow

- Expertise in Perl, TCL language is a plus

- Previous experience in QC flow is a plus

Women-friendly workplace:

Maternity and Paternity Benefits

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