Verification Designer - System Verilog/SoC Verification (4-6 yrs)
- Relevant industry experience in the field of functional verification
- Proficient in digital logic design & strong analytical ability
- Experience in IP or SoC verification including test plan development
- Expert in developing test bench/test case using System Verilog & UVM/OVM
- Prior experience with code coverage, functional coverage & assertions is desired
- Exposure to GLS or low power designs is an added advantage
- Knowledge of CPU/ GPU/ high-speed protocols is a great plus
- Good communication skills
Interested candidates can apply here.
Candidates who can join immediately are preferred.