Recruitment Specialist at ThinCI Semiconductor Technologies India Pvt Ltd
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ThinCI Semiconductor - Senior Engineer - DFT/ASIC/MBIST (4-8 yrs)
DFT - Design for Test [Sr Engineer]
Location : Hyderabad
Job Type : Permanent/Fulltime
Job Overview :
- ThinCI is a young start-up pioneering in AI area with specializations in Machine learning and Deep learning.
- GSP is highly complex and high throughput IP used for Vision and Machine Learning applications.
- The DFT engineer is responsible for implementing the Design for Test (DFT) features for ThinCI's unique IP, Graph Streaming Processor (GSP).
- The ideal candidate would work with the DFT and Functional architects to understand the DFT/DFx features and implement them.
- He/she should be familiar with industry standard DFT methodology and works very closely with the RTL Designers and Physical Design teams.
- Candidate should have good knowledge of the ASIC flows and understand the functional design along with DFT mode operations.
- The candidate should be well versed with Automatic Test Pattern Generation (ATPG), Memory BIST and Logic Built-In Self-Test (LBIST) techniques.
Desired profile :
- The candidate should have 4+ Years of experience thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory.
- Experience with any test tools such as FastScan and TestKompress is highly desirable.
- Scan/ATPG, knowledge of industry standard DFT features, simulation debug, MBIST
Key responsibilities include :
- Responsible for DFT implementation including JTAG, MBIST and SCAN, Boundary SCAN.
- Generate DFT related timing constraints and work with PD team for timing closure
- Generate and verify DFT structural patterns and functional patterns
- Design and implement other DFX (debug, characterization, yield etc) logics
- Interfacing with the design teams to ensure DFT design rules and guidelines are met
- The person should have experience in timing concepts.
- Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques
- Simulating and verifying the ATPG and LBIST patterns
- Working with the product engineering teams on the delivery of manufacturing test pattern
- Developing, enhancing and maintaining scripts as necessary
- DFT design VC_LINT and CDC violation analysis, Spyglass check;
- Synthesize and Pre-physical netlist LEC check;
Experience : 4 - 8 years working experience in DFT design;
Qualification : MS/BE degree of EE
Required Skillset :
- Familiar with DFT design and working model at JTAG IEEE1149, BC1500;
- Familiar with MBIST insertion and memory repair working strategy;
- Can solve the simulation and flow issue independently;
- Can solve the scan insertion and DRC issue;
- Experience of completing multiple tape outs and exposure to chip bring-up
- Experience working with Systems/Production teams to solve post-si issues and improve manufacturing yield
- Communication skills: good oral, written skills.
- Desirable Experience - GPU design, ARM based SOCs, multimedia, bus interface blocks
- Initiative and enthusiasm and good team player;
- Problem Solver and Detail oriented;
ThinCI is an innovative computing platforms company, developing ground-breaking products for the rapidly expanding Deep Learning, Artificial Intelligence and Ultra-Big-Data Processing Markets. Based on our proprietary Graph Streaming Processor (GSP) computing architecture, we are developing a range of next-generation hardware computing platforms to bring true task parallel computing to the broad market.
With our focus on ultra-power-efficient computing and lowest-in-class latency, our comprehensive deep-learning systems (chips + systems + software) are being adopted across industries from automotive to consumer.
We are used at scale from edge computing inference to massive Machine Learning farms, and in applications from sensor fusion to advanced neural network engines.
To know more Please visit www.thinci.com
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