Tessolve - Verification Engineer - System Verilog/DDR (3-8 yrs)
SOC/ IP Verification
Business Unit : VLSI Digital
Exp : 3+ to 8 years
No of Position: 10
- The ideal candidate should be a hands-on expert in verification using System Verilog.
- Experience with verification methodologies such as UVM/OVM is required, and a strong understanding of UVM is preferred.
- Proficient in protocols - PCI-Express, RapidIO, NVM Express, LP DDR2/LP DDR3, AXI, AHB, USB, HDMI, MIPI, & ethernet.
Qualification - Any Engineering Degree or equivalent practical experience