Manager - Talent Acquisition at Tessolve Semiconductor Pvt Ltd
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Tessolve - RTL Design Engineer - Synthesis/PCI-e (4-12 yrs)
Job Description :
- Exposure and coding level experience in Verilog, VHDL at least 5yrs.
- Experience in DC Synthesis, Linting, CDC (CDC is added advantage not compulsory)
- Design experience in Microarchitecture at least should have done three sub-blocks in 5yrs span.
- Protocol exposure and have involved in the design of any these blocks PCIE, USB3, SATA3.
- Bus protocols any Intel specific bus or AHB must and added advantage if AXI present.
- Block Level test bench exposures in Verilog for the Micro-Architecture that is carried out by the candidate.
- The Microarchitecture can be either in FPGA/ASIC (ASIC added advantage) but dealt with multiple clock domain design.