Manager - Talent Acquisition at Tessolve Semiconductor Pvt Ltd
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Tessolve - Memory Layout Design Engineer - EDA Tools (2-12 yrs)
Desired Experience : 2 Years to 12 Years of relevant experience.
Educational Qualification : Bachelor or Master Degree in Engineering.
Job Description memory Layout :
- Mask design work on various building blocks of SRAM or Register file design .
- Drawing memory core arrays with proper termination at edges, corners and straps.
- The top level integration of memory instances in memory compiler environment.
- DRC, LVS, density clean-up of memory instances across memory compiler space. The IR/EM testing and fixes of memory instances.
Required Experience :
- Hands on experience in Memory leaf cell layout read/write controls, IO block, power gate cells, spacer cells, overlay cells, sense amplifiers Architecture development, EM,IR, area intensive layouts, Quality checks (QC)
- Work experience in deep sub-micron technologies like 45nm, 32nm, 28nm, 20nm, 16nm and below .
- Good understanding of the issues in the higher technologies
EDA Tools : Cadence, Calibre & Problem Solving Capability Ability to Listen, take instructions & participate in teams Learn for knowledge and growth, Positive Work Attitude, Knowledge Sharing capability
Good to have : Scripting knowledge on perl
- Quality of work to be first-time-right in all accepted tasks & deliveries
- Team leading experience
- Good Presentation Skills