09/05 Sudharsan G
Manager - Talent Acquisition at Tessolve Semiconductor Pvt Ltd

Views:34 Applications:3 Rec. Actions:Recruiter Actions:0

Tessolve - IO Layout Engineer - CMOS/DDR (4-8 yrs)

Bangalore Job Code: 442151

Job Description :

- Good Knowledge about IO Layout, should have work experience on 28nm (Below 28nm is highly preferable)

- Good Working Experience on Cadence Virtuoso LE/XL, Calibre/Assura/Hercules DRC, LVS.

- Good Understanding of ESD/Antenna/Latch up/EM effects and their implementation in Layout Design.

- Sound knowledge of IO blocks like Design of the Transmitter /Receiver Blocks, Level Shifters.

- Exposure to DDR IOs, XTAL IOs an added advantage.

- Very Good CMOS fundamental.

- Good Communication Skill

- Skill/Perl programming knowledge is an added advantage.

Qualification : Any Engineering Degree or equivalent practical experience.

Add a note
Something suspicious? Report this job posting.