05/08 Sudharsan G
Manager - Talent Acquisition at Tessolve Semiconductor Pvt Ltd

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Tessolve - FPGA Prototyping Design Engineer - Synthesis/SoC (4-10 yrs)

Bangalore/Hyderabad Job Code: 476844

Job Responsibilities and Requirements :

- This role includes RTL design, verification, FPGA partitioning and implementation, and lab-based bring up of the SoC on FPGAs.

- Recent FPGA experience including implementation, synthesis (Synplify), timing closure (Vivado/ISE).

- Ability to architect, implement and verify modules for FPGA interconnect.

- Proficient in Verilog, Perl, and Make

- Both simulation-based verification and lab-based debug skills on FPGAs.

- Experience with a source control system, such as Perforce.

- Must be familiar with both Linux and Windows environments

- Hands on with lab FPGA debug methodologies, such as ChipScope, Identify or others.

- Hands on experience with lab debug the equipment, such as oscilloscopes and logic analyzers.

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