HR Executive at Tessolve Semiconductor
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Tessolve - FPGA Emulation Engineer - Synthesis/RTL Design (3-10 yrs)
- This position primary focus on Emulation and FPGA prototype of Complex SOC on Emulation platform.
- He/she should be able to validate logical blocks of the SOC and identify bugs, debug and resolve them with greater quality.
Minimum Qualifications : Candidate should have 3-10 years of related experience in SOC Emulation.
Domain : Emulation on USB,PCI, DDR, ARM, PCIE, Ethernet, Wireless, SATA (any one)
Emulation Job Description :
- Creates Emulation models from RTL design using Emulation tools.
- Strong expertise into Emulation with Zebu, Palladium, Veloce platforms at least one of them.
- Should have good knowledge in implementing Bigger designs in multiple FPGA's/HAPS platforms.
- Familiarity with FPGA synthesis & PAR tools.
- System-On-Chip Pre-Silicon emulation builds creation & bring-up on Emulation platforms.
- Good Knowledge on protocols : PCIe,USB, Memory, Low and High speed protocols etc
- Hands on experience Chipscope, lab tools like Logic Analyzers, Oscilloscopes, JTAG / Lauterbach Trace 32 etc.
- Good programming skills i.e. Verilog,VHDL,SV, C/C++ is must.
- Knowledge of TCL, PERL,Python a definite plus.
- Knowledge on Validation is an added advantage.
- Good written and oral communications skills required.