Team Lead- HR at Tessolve Semiconductor
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Tessolve - DFT Engineer - Verification/ATPG (3-6 yrs)
Here are the requirements :
1. Minimum 3 yrs experience with DFT implementation and verification
2. Experience required with implementation tools like Mentor Tessent Fastscan, Testkompress or Synopsys DFT compiler and Tetramax
3. Sound knowledge of ATPG, coverage analysis, EDT compression etc.,
4. Experience with Memory BIST implementation and verification
5. Sound debug skills to debug simulation failures at RTL-level and gate-level
6. Exposure to Static timing in DFT modes to debug constraint issues and review/analyze timing reports
Kindly apply here.
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