Manager - Talent Acquisition at Tessolve Semiconductor Pvt Ltd
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Tessolve - ASIC Design/Verification Engineer (5-10 yrs)
Job Description :
- As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clock structures.
- You should be able to engage with multiple teams and design the clock structure to satisfy all the architectural constraints.
- Your understanding of general verification principles will be valuable to verify the design of the clock.
- Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams.
- You will use Perl to improve the productivity of the above teams.
- You will collaborate with Software and product group to debug clock silicon bugs in our new products.
- You will understand and design clocking structures to overcome sub-micron design challenges.
- You will also identify improvements in the current design and propose and implement new ways to improve the efficiency in the GPU clocking design.
Minimum Requirements :
- BS or MS (preferred) in EE, with a minimum of 5 years of relevant industry work experience
- Experience in RTL design (Verilog), verification and synthesis
- Strong coding skills in Perl or other industry-standard scripting languages
- Ability to interface with many groups
- Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus
- Prior experience in implementing on-chip clocking networks is a plus