Manager - Talent Acquisition at Tessolve Semiconductor Pvt Ltd
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Tessolve - AMS Verification Engineer - C/C++/Verilog (2-7 yrs)
- 2 - 7 years of experience in Analog and Mixed Signal (AMS) verification
- Hands-on experience in C/C++ based verification and SV/UVM based verification
- Strong fundamental knowledge of analog circuits behavior
- Ability to write models using Verilog/Verilog AMS
- Understanding complete verification flow
- Experience in SV/PSL assertion methodology
- Hands-on experience on Cadence and other tool flows
- Gate level simulation experience is an advantage.
- Good Communication skills.
- Strong problem solving and analytical skills