Technical Lead - Synopsys/Timing Closure/Floor Planning (4-15 yrs)
- Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs.
- Schematic (LVS) checks, Antenna checks.
- Should have worked on 45nm or lower node designs with adv. low power techniques such as Voltage Islands, Power Gating and substrate-bias
Required Skills :
- Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure
- Extensive experience and detailed knowledge in Cadence or Synopsys physical Design Tools.
- Expertise in scripting languages such as PERL, TCL
- Strong Physical Verification skill set.
- Static Timing Analysis in Primetime or Primetime-SI
Desired Skills :
- Provide technical guidance, mentoring to physical design engineers
- Interface with front-end ASIC teams to resolve issues
- Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques
- Excellent communication skills
- Timing closure on DDR2/DDR3/PCIE interfaces