08/03 Shash
CEO at Vhunt4U

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Technical Lead - DFT Implementation (5-10 yrs)

Bangalore/Hyderabad Job Code: 420162

- 5+ years of relevant work expertise in DFT.

- Scan insertion & ATPG- Pattern Simulation with and without timing annotation and debugging simulation mismatches (Cadence Incisive).

- Familiarity with WGL/TDL file formats.

- Good skills in Scan compression techniques and Logic BIST.

- Exposure to Memory BIST insertion tools (Preferably LogicVision MBIST).

- Good experience in Boundary Scan, JTAG concepts, Core testing using P1500.

- Should have basic understanding of Tester requirements.

- Should be good at doing synthesis and timing (RC and PT/Tempus).

- Knowledge of formal verification using LEC.

- Exposure to SoC level DFT will be a plus.

- Experience on low power DFT is an added advantage.

- Handling large DFT teams is an added advantage

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