24/09 Lr. Gangadhara Shiva
AVP - Search, Selection & RPO at AdAstra Consultants Pvt Ltd

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Synthesis/STA Lead - Timing Closure/DFT (5-10 yrs)

Hyderabad Job Code: 364533

Position : Synthesis / STA Lead

Qualification : B.Tech / B.E / M.Tech / M.E

Experience : 5 to 10 yrs

Job Location : Hyderabad

Roles & Responsibilities :

- Hands on experience with Logic Synthesis & Timing Analysis of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)

- Lead Synthesis and STA activities on SoC designs with expertise in Constraints creation, CDC checks, Logical/Physical synthesis, Formal verification and Pre/Post Layout Timing closure

- Expertise in Flat/Hierarchical SoC design synthesis while meeting PPA targets

- Expertise in Timing constraints creation for FE/BE, time budgeting, constraints coverage analysis, Timing closure techniques in MMMC environment

- Work closely with CAD teams and involve in synthesis/timing methodology development and improvement

- Own SoC synthesis/timing activities while managing a team of 5-10 engineers

Desired Skills and Experience :

- B. Tech. / M. Tech. with 5-10 years of experience in Synthesis/STA

- The candidate should be able to work with and lead a team of engineers working on FE design (Synthesis, DFT, FV, STA) and Timing closure on an SOC design

- Should have handled Synthesis/STA for atleast 2-3 SoC designs on lower technology nodes

- Excellent understanding of timing closure techniques & SI analysis/fixes in lower technology nodes in high speed designs with DDR, Serdes, USB interfaces

- Experience on LP synthesis and Static power checks

- Experienced in industry standard tools viz. Synopsys (DC/DC-T/DC-G, PT, GT, Formality), Cadence (RTLC, RCP, LEC, Tempus)

- Knowledge in TCL, Perl scripting is a must

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