Talent Acquisition Member at Sventl
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Sventl - STA Synthesis Engineer - ASIC/Timing Closure (4-8 yrs)
SVENTL INDIA is hiring for STA Synthesis.
ASIC timing constraints generation and timing closure.
Job Description :
- Expertise in STA tools (Primetime) and flow.
- Knowledge of timing corners/modes, process variations and signal integrity related issues.
- Hands on experience in timing/SDC constraints generation and management.
- Proficient in scripting languages (Tcl and Perl).
- Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools.
- Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups.
- Self-starter and highly motivated.
Roles & Responsibilities :
- Create/update timing constraints chip level timing constraints
- Should be able to run synthesis analyze timing violations
- Debug the issues - identify design and constraint issues
- Make edits timing constraints
- Create TCL automation scripts for DC/PT tools using attributes
Required Skills :
- Should be an expert in chip / block level STA
- Perl/tcl experience to parse reports/logs and highlight issues
- STA / Synthesis experience in Synopsys/Cadence tool flows.