02/04 Ramya Harika
Talent Acquisition Member at Sventl

Views:150 Applications:4 Rec. Actions:Recruiter Actions:1

Sventl - DFT/Verification Engineer - Physical Layer/VHDL (4-10 yrs)

Singapore Job Code: 428564

SVENTL is hiring for DFT with VERIFICATION ENGINEER

Job Description :

- Definition/Development of Design-for-Testability(DFT) concept.

- Scan pattern generation (SAF and TDF), coverage analysis and re-imulation.

- Implementation, verification and documentation mixed signal IP tests such as PCIe PHY, PLL etc.

- Test pattern generation, pattern re-simulation and first silicon support.

Requirements :

- Experience in Design for Test (DFT) of large, lower geometry SOC designs.

- Experience in DFT concepts, test mode.

- Good knowledge in Boundary Scan, ATPG Scan, [Automatic test pattern generation tools]

- Proficiency in VHDL/Verilog coding, testbench setup, test case creation and verification.

- Proficiency in mixed signal IP verification such PCIe Phy, PLL etc.

- Experience with industry standard tools for DFT and Verification (Synopsys, Cadence).

- Proficiency high level programming and scripting Languages such as - C-, - C++-, Perl

- Knowledge or Experience in Test development and Product engineering will be added advantage.

Also able to handle :

- Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level

- Develop IP level/SoC level test plans based on the design/architectural specs.

- Coverage Analysis and Coding

- Experience in ASIC Verification and Methodologies

- Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies is Mandatory.

Women-friendly workplace:

Maternity and Paternity Benefits

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