Talent Acquisition at Sventl
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Sventl - DFT Engineer - VHDL/Verilog (4-10 yrs)
SVENTL is hiring for DFT Engineers.
Job Description :
- Definition/Development of Design-for-Testability (DFT) concept.
- Scan pattern generation (SAF and TDF), coverage analysis and re-imulation.
- Implementation, verification and documentation mixed signal IP tests such as PCIe PHY, PLL etc.,
- Test pattern generation, pattern re-simulation and first silicon support.
- Experience in Design for Test (DFT) of large, lower geometry SOC designs.
- Experience in DFT concepts, test mode.
- Good knowledge in Boundary Scan, ATPG Scan [Automatic test pattern generation tools].
- Proficiency in VHDL/Verilog coding, testbench setup, testcase creation and verification.
- Proficiency in mixed signal IP verification such PCIe Phy, PLL etc.
- Experience with industry standard tools for DFT and Verification (Synopsys, Cadence).
- Proficiency in high level programming and scripting languages such as - C, C++-, Perl
- Knowledge or Experience in Test development and Product engineering will be an added advantage.