05/11 Ramya Harika
Talent Acquisition Member at Sventl

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Sventl - DFT Engineer - ATPG/LBIST (3-11 yrs)

Bangalore/Chennai/Hyderabad/Noida/Pune Job Code: 377774

SVENTL INDIA is hiring for DFT Engineers

DFT engineer with good analysing capabilities with the below

skills : Scan insertion & ATPG - Pattern Simulation with and without timing annotation and debugging simulation mismatches (Cadence Incisive). 

- Familiarity with WGL/TDL file formats. 

- Good skills in Scan compression techniques and Logic BIST.

- Exposure to Memory BIST insertion tools (Preferably Logic Vision MBIST).  

- Good experience in Boundary Scan, JTAG concepts, Core testing using P1500. 

- Should have basic understanding of Tester requirements. 

- Should be good at doing synthesis and timing (RC and PT/Tempus). 

- Knowledge of formal verification using LEC. 

- Exposure to SoC level DFT will be a plus.

- Experience on low power DFT is an added advantage.

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