01/03 Ramya Harika
Talent Acquisition Member at Sventl

Views:189 Applications:15 Rec. Actions:Recruiter Actions:0

Sventl - ASIC Verification Engineer - UVM/Perl/TCL (3-9 yrs)

Bangalore Job Code: 417475

SVENTL INDIA is hiring for ASIC VERIFICATION ENGINEER

Job Role : Verification Engineer.

- Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level

- Develop IP level/SoC level test plans based on the design/architectural specs.

- Coverage Analysis and Coding

- Run simulations & regressions, debug test failures to identify test case issues & RTL design issues

- Define and develop block/full chip level verification environment and its components

Required Skills :

- 3 - 9 & above years of experience in ASIC Verification and Methodologies

- Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies

- Good understanding of RTL concepts

- Good understanding of AHB/AXI protocol

- Expertise in PCI-e/ USB/ Ethernet/ Switch protocol is an added advantage

- Knowledge of Perl/TCL is Must

- Good communication skill

This job opening was posted long time back. It may not be active. Nor was it removed by the recruiter. Please use your discretion.

Women-friendly workplace:

Maternity and Paternity Benefits

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