02/11 Naga Sree
Talent Acquisition at Sventl

Views:83 Applications:1 Rec. Actions:Recruiter Actions:0

Sventl - ASIC Verification Engineer - System Verilog/PCI-e (4-8 yrs)

Bangalore/Chennai/Hyderabad/Noida/Pune Job Code: 377196

SVENTL is hiring for Physical Design Engineer.

Roles & Responsibilities :

- Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level

- Develop IP level/SoC level test plans based on the design/architectural specs.

- Coverage Analysis and Coding

- Run simulations & regressions, debug test failures to identify test case issues & RTL design issues

- Define and develop block/full chip level verification environment and its components

Required Skills :

- 4-8 & above years of experience in ASIC Verification and Methodologies

- Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies

- Good understanding of RTL concepts

- Good understanding of AHB/AXI protocol

- Expertise in PCI-e/ USB/ Ethernet/ Switch protocol is an added advantage

- Knowledge of Perl/TCL is Must

- Good communication skill

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