29/10 Ramya Harika
Talent Acquisition Member at Sventl

Views:103 Applications:4 Rec. Actions:Recruiter Actions:0

Sventl - ASIC Verification Engineer - RTL Design/System Verilog (4-10 yrs)

Bangalore Job Code: 375628

SVENTL INDIA is hiring for ASIC Verification Engineers.

- Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level

- Develop IP level/SoC level test plans based on the design/architectural specs.

- Coverage Analysis and Coding

- Run simulations & regressions, debug test failures to identify test case issues & RTL design issues

- Define and develop block/full chip level verification environment and its components

Required Skills :

- 5+ years of experience in ASIC Verification and Methodologies

- Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies

- Good understanding of RTL concepts

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