IT Recruiter at Infinity HR Consulting Services
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Static Timing Analysis Engineer - Synthesis (6-15 yrs)
Job Title : STA (Static Timing Analysis) Engineer
- Responsible for block level and chip level timing analysis.
- Timing analysis of different kind of interfaces at chip level.
- Work with the design and implementation teams to develop and qualify timing constraints.
- Work on methodology development for timing analysis and timing closure.
- Creation, enhancement and maintenance of different timing related scripts.
- Work closely with the physical design engineers to resolve implementation related timing issues.
- Create methodologies for customized timing checks for different IPs, interfaces etc.
- Validation of library timing data (qualification of libraries).
- 7-10 years of hands-on experience in timing analysis.
- Experience in doing SoC level timing analysis.
- Should be familiar with timing analysis for hierarchical designs.
- Familiarity with different types interfaces like PCIe, SATA, USB, DDR etc.
- Worked on technology nodes 28nm and below.
- Familiarity with time budgeting.
- Should be proficient with Synopsys- Prime Time for timing analysis.
- Good scripting skill in Tcl and Perl.
- Familiarity with different physical design tools - preferably Cadence Encounter