Technical Recruiter at Infinity HR
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Standard Cell Characterization Design Engineer - Verilog/DFT/ATPG (7-13 yrs)
Role Purpose :
- The Physical IP Division inside ORGANIZATION creates Physical IPs of various types like Standard Cells, Memory and Interface which are extensively used by thousands of IC designers around the world to design leading edge chips. We are currently marketing and developing solutions from 180nm to 7nm and research work on 5nm solutions is happening at various ORGANIZATION design centres worldwide.
- A dedicated team of experienced professionals in software, methodology and flow development aids this process of creating Physical IPs for leading edge chips. Forming part of the ORGANIZATION Physical IP Division, the Modelling and Methodologyteam develops Front end models for Standard Cells, Memory and Interface physical IP as well as creates methodologies to validate the physical IP.
- The front-end model development involves creation of Simulation, DFT, ATPG, Low Power views which gets used during SoC Implementation. The group also focuses on methodology development in the areas like Correlation, Simulation, Synthesis, DFT, ATPG, Logic Equivalence, Static Timing Analysis, Power Analysis, Place and Route etc. to make our IP robust while reducing the development cost.
Role & Responsibilities :
- The candidate will be responsible for leading a small team in doing development and maintenance of the front-end views like Verilog simulation models, DFT and ATPG models, UPF and CPF models, etc for Standard Cells and Interface physical IP.
- The role requires interaction with accomplished circuit designers across worldwide to resolve engineering dependencies.
- Candidate would also be responsible for being an interface between the engineering teams, external customers and EDA partners to track resolution of issues associated with front end views
2. Methodologies :
- The candidate would be responsible for driving methodology development for Physical IP generation and validation by understanding the IP view requirement from SoC implementation perspective.
- He is expected to work closely with engineering team as well as EDA partners for requirement gathering and work with software team for the implementation of the flows in order to create most efficient and high-quality solutions for the engineering community.
- He will also be responsible for driving engagements with EDA partners to explore new EDA solutions impacting our Physical IP deliverables for Logic and Interface IPs.
Qualification & Experience :
- Bachelors or Master's Degree in Electronics Engineering or equivalent
- 7-12 years of engineering experience in area of Physical IP development
Characteristics & Requirements :
- Quick learner, good problem solving and debugging skills
- Willingness to be flexible and accept new challenges
- Capable of leading a small team
- Ability to work cross sites and cross teams
- Ability to engage with external customers and EDA partners
- Good analytical and reasoning skills
- Enthusiastic and self-motivated
Essential Technical Experience :
- Good understanding of digital circuits fundamentals and SoC concepts
- Experience with Verilog modelling and verification
- Experience with Frontend flows like Simulation, Synthesis, ATPG and Logic Equivalence
- Familiar with Analysis tools like Timing, Power, Noise, etc
- Familiar with source control systems like Synchronicity or SVN
- Working knowledge of scripting tools (TCL, Perl)
Desirable Technical Experience :
- Experience with System Verilog based verification
- Working knowledge of CPF/UPF - Low power flows
- Working knowledge of Spice simulation
- Familiar with Backend tools like Place and Route, Extraction, etc.