22/08 Priya Gupta
Senior Talent Scout at Intileo Technologies

Views:36 Applications:1 Rec. Actions:Recruiter Actions:0

STA/Synthesis Lead - Soc/RTL (8-15 yrs)

Greater Noida Job Code: 483294

ROLE PURPOSE

The incumbent will be a Technical Leader who will be involved in Complete Responsibility of constraints, timing synthesis with full responsibility of the SOC, along with - LEADING A PROJECT TEAM CONSISTING OF 5 - 8 ENGINEERS- for innovative solutions in the field of Sensors, Consumer Durable Products & Cars.

A TECHNICAL MENTOR TO THE YOUNGER ENGINEERS & BE ABLE TO GUIDE THEM THROUGH THE PROJECTS.

DETAILED JOB DESCRIPTION :

- Responsible for definition and executing of Synthesis, Const. generation, CTS and timing closure for complete SOC and Blocks.

- Understanding system specification with RTL designers/DFT/architectures and generating constraints for synthesis and PnR. Partitioning constraints for SOC and blocks.

- Also need to lead or coordinate various activities of SOC Implementation with-in the team and interaction with CAD team, Design teams and Customer.

MUST HAVE SKILLS :

- Expert in developing chip constraints working with RTL and DFT teams

- Synthesis and STA Expertise with synopsys/Cadence tools

- Knowledge of Netlist to GDSII flow

- Should have good understanding of verilog/VHDL

- Exposure to low power techniques

- Knowledge of tcl and perl scripting is a must

- Block Level Synthesis

- SOC Synthesis

Women-friendly workplace:

Maternity and Paternity Benefits

Add a note
Something suspicious? Report this job posting.