SOC Verification/IP Verification Engineer - System Verilog/UVM/OVM (2-5 yrs)
Job Title / Designation : SOC Verification/IP Verification Engineer
Job Description :
- Expert user of System Verilog with good experience in building verification environment using VIPs.
- Should have worked on Test Bench components like drivers, monitors and scoreboards in System Verilog.
- Should be comfortable writing assertions for protocol validation.
- Must have good exposure to IP or SoC level verification.
- Must have experience in UVM or OVM. Added advantage if and if having knowledge of AXI, AHB, SPI, UART, DDR, USB, I2C, etc. along with experience in creating Verification plans
- In depth Knowledge of System Verilog and OVM
- Designing bus functional models, scoreboards, coverage, assertions, etc.
- SOC/IPVerification Experience- Mandatory.
- Experience in protocols like ARM, PCIe, Bluetooth, Wireless will be a definitive advantage.
Minimum/Maximum/ Work Experience Required : 2-5 Years
Location(s) of Job : Bangalore - Whitefield
Annual CTC : Open
Minimum Education Requirements : B.Tech/BE/M.Tech/ME in ECE/EEE/ Electronics
No of rounds of Interviews : 3-4
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